1. Field of the Invention
The present invention relates to the formation of capacitors for integrated circuit memories and particularly to methods of forming high capacitance structures in a high production volume manufacturing environment.
2. Description of the Related Art
In dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Most often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one, or vice versa. The surface area of the electrodes of the memory capacitors determines the amount of charge that can be stored on each of the capacitors for a given operating voltage, for the electrode separation that can reliably be manufactured, and for the dielectric constant of the capacitor dielectric used between the electrodes of the charge storage capacitor. Read and write operations are performed in the memory by selectively coupling the charge storage capacitor to a bit line to either transfer charge to or from the charge storage capacitor. The selective coupling of the charge storage capacitor to the bit line is typically accomplished using a transfer field effect transistor (FET). The bit line contact is typically made to one of the source/drain electrodes of the transfer FET and the charge storage capacitor is typically formed in contact with the other of the source/drain electrodes of the transfer FET. Word line signals are supplied to the gate of the FET to connect one electrode of the charge storage capacitor through the transfer FET to the bit line contact facilitating the transfer of charge between the charge storage capacitor and the bit line.
There is a continuing trend toward increasing the storage density of integrated circuit memories to provide increased quantities of data storage on a single chip. Higher density memories provide storage that is generally more compact and is often cheaper on a per bit basis than an equivalent amount of storage provided on plural chips. It has generally been possible to provide these higher levels of storage at equivalent or improved levels of performance as compared to the earlier, less dense memory chips. Historically, the density of integrated circuit devices has been increased in part by decreasing the size of structures such as wiring lines and transistor gates and in part by decreasing the separation between the structures that make up the integrated circuit device. Reducing the size of circuit structures is generally referred to as decreasing the "design rules" used for the manufacture of the integrated circuit device.
Applying reduced design rules to a DRAM reduces the substrate surface area that can be devoted to the charge storage capacitor of the DRAM. Thus, applying reduced design rules to conventional planar capacitor designs reduces the amount of charge (i.e., capacitance) that can be stored on the charge storage capacitor. Reducing the amount of charge on the capacitor leads to a variety of problems, including the potential loss of data due to greater susceptibility to decay mechanisms and to charge leakage. This greater susceptibility to charge loss may cause the DRAM to require more frequent refresh cycles, which are undesirable since the memory may be unavailable for data storage and readout transactions during refresh activities. In addition, reduced levels of charge storage might require more sophisticated data readout schemes or more sensitive charge sensing amplifiers. Thus, modem DRAMs require increased levels of capacitance in reduced substrate area DRAM cells. To this end, a variety of very complex capacitor structures having three dimensional charge storage surfaces have been proposed. In general, these complex capacitor structures are difficult to manufacture. This is particularly true when the requirements are taken into account for forming such capacitor structures in a high throughput manufacturing environment in a manner compatible with high yields.
One strategy that has been adopted in attempting to improve the DRAM cell capacitance has been to incorporate hemispherical grained polysilicon within the charge storage capacitor. Most current DRAM capacitor designs incorporate conventional polysilicon within both electrodes of the capacitor. While the conventional polysilicon can be shaped into very complex shapes, its surface is essentially smooth. Hemispherical grained polysilicon (HSG-Si) is a particular form of polysilicon that has a rough surface when deposited under carefully controlled conditions and which can be incorporated on the surface of the capacitor electrode to increase the surface area of the electrode. By providing a layer of hemispherical grained polysilicon on one capacitor electrode, the capacitance of a given DRAM charge storage capacitor can be increased by a factor of approximately 1.8 times.
There are, on the other hand, disadvantages to the use of HSG-Si in DRAM capacitors. HSG-Si can have unpredictable surface properties that can reduce capacitance or reduce the stability of the capacitor. In addition, it can be difficult to adequately dope HSG-Si during deposition. Thus, in addition to the precise control required in the deposition process, it is typically necessary to include a separate doping step to ensure that the HSG-Si layer has an appropriate level of conductivity for use on the surface of the capacitor electrode. The processing difficulty associated with using HSG-Si on the surface of a polysilicon capacitor electrode limits is applicability to high volume manufacturing processes. In many instances, the gain in capacitance achieved through use of HSG-Si in a capacitor does not justify the added expense and reduced yields associated with its use.
It is an object of the present invention to provide increased levels of charge storage capacitance for an integrated circuit capacitor of the type that might be used in a memory. It is a further object of the present invention to provide increased capacitance in a highly manufacturable manner.